CPU bus

A machine-check mechanism has detected a CPU or bus error .

机器检查机制检测到CPU或总线错误。

In monitoring and control system of the simulator , the SCM system is defined as including : frequency oscillator , watchdog and EEPROM , RS232 interface , the CPU data bus and address bus driver latch .

在模拟器测控系统中，把单片机系统定义为包括：主频振荡器、看门狗和EEPROM、RS232接口、CPU、数据总线驱动器和地址总线锁存器。

Solution Scheme for On-Chip Protocol Communication Between Telecom Specific CPU and PCI Bus

通信专用CPU与PCI总线实现芯片内协议通信的解决方案

A network founded on this CPU and RS-485 bus line has higher ratio of performance to price .

使用这种CPU和RS-485总线建立起的网络具有较高的性价比。

Completion stealing is a problem difficult to deal with in protocol communication between CPU and PCI bus .

事务窃取一直是困扰CPU与PCI总线实现协议通信的难题。

Collecting channels stored the collected data into their respective caches , which were disposed by CPU through system bus .

各采集通道把采集数据存入各自缓存，由CPU通过系统总线处理。

Besides the high cost and poor extensibility , the performance of traditional image compression and processing systems based on industrial computers are limit to the CPU speeds and bus bandwidths .

传统的基于工控机与采集卡的图像压缩处理系统，其性能受到工控机CPU速度和总线带宽的限制，且成本较高，可扩展性较差。

According to verified objects in different areas and verified modules in different levels , there are many function verification directions , such as CPU , on-chip bus , memory and so on .

根据不同领域的验证对象和不同层次的验证模块，功能验证有很多研究方向，如针对CPU、片上总线、存储器等的验证。

Realization of the High-speed Communication of Multi CPU Systems on STD Bus

多CPU系统在STD总线上高速通讯的实现

Configuring FPGA with CPU Based on ISA Bus

基于ISA总线FPGA的配置

Traditionally only one CPU is in the bus architecture , With the development system theory , multi-CPU architecture tends to be more advantageous and attractive .

但是随着系统的发展，多CPU体系是更大规模发展的趋势，但总线结构的原始构思是基于单一CPU的，传统总线结构无法满足发展的需求。

The use of CPLD makes the stucture of the system more integrated . The 32-bit data acquisition system , the speed of data transmission is faster , the CPU resource and PCI bus resource are spared .

同时采用通用大规模集成器件（CPLD），设计实现了32路数字采集通道，提高了数据传送速率，节约了CPU资源和PCI总线资源。

Integrally , the RISC CPU has BIU ( Bus Interfacing Unit ), IDU ( Instruction Decoding Unit ) - . ALU ( Arithmatic & logic Unit ), MMU ( Memory Management Unit ) etc.

从整体方面来说，整个微处理器大致分为BIU（总线接口单元）、IDU（指令译码单元）、ALU（算术逻辑单元）、MMU（存储管理单元）等等。